An accurate measure of the jitter characteristics of a signal waveform or, alternatively, a measure of the timing variation between a signal waveform and a reference waveform can yield important information relating to the performance of the source of the signal waveform. Accordingly, the performance of timing and jitter measurement devices is a key factor in being able to accurately characterize the performance of a signal waveform source (e.g. a phase-locked loop). To this end, much recent effort has been devoted to improving the performance and resolution of such timing and jitter measurement devices.
Performing a jitter measurement on a data signal with sub-gate resolution can be achieved using two delay chains feeding into the clock and data lines of a series of D-latches as shown in FIG. 1. Such a structure has come to be known in the art as a Vernier Delay Line (VDL). Here it is assumed that the clock signal is jitter-free. In this case, then, the jitter measurement may be defined as a measure of the time interval between the rising edge of the data signal and the rising edge of the clock signal. The symbols τf and τs represent the respective propagation delays of the buffers interconnecting each stage of the VDL. As the propagation delays of the clock and data paths differ by an amount of Δτ=(τs−τf) the time difference between the rising edges of the data and clock signals will correspondingly decrease by Δτ after each stage of the VDL. After each stage, the phase relationship between these two rising edges is detected and recorded by a corresponding D-latch. A logical 0 will result when the clock signal leads the data signal, whereas a logical 1 will result when the data signal leads the clock signal. The output of each D-latch is passed to a counter circuit, which simply counts the number of times the data signal leads the clock signal (i.e., the number of logical 1's) with a delay difference set by its position in the VDL.
By design, the data signal in FIG. 1 will be made to always lead the clock signal at the input of the VDL by incorporating an additional delay (not shown) after the clock input. Subsequently, as the data and clock signals progress through each stage of the VDL, a point will be reached where the data signal will start to lag the clock signal on account of the extra delay, Δτ, in its signal path. All D-latches subsequent to this point will register logical 0, whereas all D-latches before this point will register a logical 1. In any event, a counter after each stage of the VDL is used to register the state of each corresponding D-latch.
As the phase between the data and clock signals at the input of the VDL is a random variable, each time the measurement is performed, a different set of D-latches are set to a logical 1 level and the corresponding counters begin to register different values. In the case of the first counter, for example, its count value reflects the number of times the rising edge of the data signal is ahead of the rising edge of the clock signal with a delay greater than Δτ. Likewise, the counter in the next stage will correspond to the number of times the rising edge of the data signal leads the rising edge of the clock signal with a delay greater than 2Δτ. In the same manner, the following stages correspond to the number of times the data signal leads the clock signal by 3Δτ, 4Δτ, and so on and forth. Statistically, these numbers can be viewed as representing the Cumulative Distribution Function (CDF) of the jitter riding on the data signal. The Probability Density Function (PDF), or what is also referred to as a histogram, can then be obtained by taking the derivative of the CDF.
Alternatively, a histogram of jitter can also be derived from the data generated by a VDL. For example, if one assumes that the period of the data and clock signal, denoted as T, is larger than the total propagation delay through an M-stage VDL, approximately Mτs if we assume τs>τf, then the outputs of all the D-latches may be combined into one bit-stream whose total count of logical 1's represents the actual time difference between the edge of the data and clock signal taken at a particular instant in time. As is shown in FIG. 2, this may easily be achieved by “OR”-ing the outputs of all the D-latches and counting the number of logical 1's over the time period T. Therefore, repeating the measurement N times enables a histogram of jitter to be similarly constructed.
An important drawback to the prior art VDL structures shown in FIGS. 1 and 2 is that measurement accuracy depends on the matching of delay elements between successive stages. Mismatches in delay elements can lead to errors in the CDF or histogram collected. In other words, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. Although careful layout techniques may help in minimizing these mismatches, they cannot eliminate them completely.
In general, Time-to-Digital Converter (TDC) using a Delay Locked Loop (DLL), Vernier Delay Line (VDL) and ring oscillator phase digitization are common techniques used to provide high-resolution timing measurements. In recent years, on-chip timing measurements, such as jitter characterization of Phase Locked Loops (PLLs), have become extremely demanding with required timing resolutions less than 100 ps In order to meet these needs, researchers have devised various schemes in which to perform on-chip timing measurements. In S. Sunter and A. Roy, entitled “BIST for phase-locked loops in digital applications”, and published in Proc. IEEE International Test Conference, pp. 532-540, 1999, an on-chip circuit consisting of a ring oscillator and a calibration circuit was reported to be able to perform timing measurements with a resolution as low as a single gate delay. Moreover, the circuit was fully synthesizable from an RTL description, as the design did not depend on matched elements. A significant improvement to sub-gate resolution was recently reported using a VDL. In this case, the timing resolution was said to be derived from the difference of two gate delays. Unfortunately, however, the reported design still depends largely on the matching of pairs of delay elements. Accordingly, a timing measurement method and system that avoids dependency on matched delay lines remains highly desirable.